1. Field of the Invention
The present invention relates to image signal processing, and, in particular, to systems for capturing, compressing, decompressing, and displaying digital images.
2. Description of the Related Art
It is desirable to provide a flexible video system for the capture, compression, decompression, and display of motion video images in a personal computer (PC) environment in real time. Such a video system is preferably capable of supporting a variety of operating modes such as the pass-through, compression, and playback modes.
In pass-through mode, a video generator (e.g., a video camera) generates video images that are processed by the video system for real-time display on a display monitor. In compression mode, the video images are compressed by the video system in real-time for storage in a mass storage device (e.g., a computer hard disk). In playback mode, compressed video images stored in a mass storage device (e.g., a CD-ROM) are decompressed and processed by the video system for display on a display monitor.
Moreover, the video system is preferably capable of displaying video images into specified windows on the display screen. This typically involves scaling and positioning all or part of the display image into the desired display window. The video system also preferably supports the merging of video images with images from graphics processors, such as an IBM Video Graphics Array (VGA) processor or a VGA compatible processor.
Referring now to FIG. 1, there is shown a block diagram of a video system 100 that performs the above-described functions. Video system 100 is exemplary of conventional video systems that implement the pass-through, compression, and playback modes. In pass-through mode, video signals generated by video generator 106 are processed by an Intel.RTM. ActionMedia-II.RTM. subsystem LOS for display on display monitor 110. In compression mode, ActionMedia-II.RTM. subsystem compresses the video data for access by host processor 102 and for storage to mass storage device 104 via host bus 114. In playback mode, host processor 102 accesses compressed video images stored in mass storage device 104 and transmits the compressed data via host bus 114 to ActionMedia-II.RTM. subsystem 108, which decompresses and processes the video data for display on display monitor 110. In either pass-through or playback mode, the video images may be optionally merged with images from graphics processor 112.
Referring now to FIG. 2, there is shown a block diagram of ActionMedia-II.RTM. subsystem 108 of video system 100. In pass-through mode, video decoder/digitizer 202 receives an analog video signal from video generator 106 of FIG. 1, decodes the analog video signal into three linear components (e.g., a luminance Y component and two chrominance U and V components), and digitizes each of the three linear component signals. The digitized data is then captured and stored to dual-port video random access memory (VRAM) 208 by capture/VRAM controller 204 via subsystem bus 216.
Pixel processor 206 then accesses the video data stored in VRAM 208, scales the data for display in the desired window of the display screen, and stores the scaled data back to VRAM 208. Display processor 20 then accesses the scaled bitmap data in VRAM 208 to generate video data for transmission to video/graphics merger 212, which optionally merges the video data with images from graphics processor 112 of FIG. 1 for display on display monitor 110.
In compression mode, the captured video data stored in VRAM 208 is accessed by pixel processor 20 via subsystem bus 216 for compression and then stored as compressed video data back to VRAM 208. Host interface 214 then accesses the compressed video data stored in VRAM 208 via subsystem bus 216 for transmission to host processor 102 of FIG. 1 via host bus 114 for storage in mass storage device 104 of FIG. 1.
In playback mode, host interface 214 receives compressed video data from host processor 102 via host bus 114 and stores the compressed data to VRAM 208 via subsystem bus 216. Pixel processor 206 then accesses the compressed data stored in VRAM 208, decompresses the compressed data, and stores a decompressed bitmap back to VRAM 208. Pixel processor 206 then accesses the decompressed bitmaD data from VRAM 208, scales the decompressed data for display, and stores a scaled bitmap back to VRAM 208. Display processor 210 then accesses the scaled bitmap data in VRAM 208 to generate video data for transmission to video/graphics merger 212, which optionally merges the video data with images from graphics processor 112 of FIG. 1 for display on display monitor 110.
Although ActionMedia-II.RTM. subsystem 108 provides the above-described operating modes and functions effectively, it still has certain limitations. For example, ActionMedia-II.RTM. subsystem 108 creates and stores complete scaled bitmaps to memory (i.e., VRAM 208) before displaying the scaled data. Moreover, those scaled bitmaps contain background pixels that are outside of the active video window pixel region (i.e., the region corresponding to actual video data). Furthermore, the display scaling implemented by ActionMedia-II.RTM. subsystem 108 is not continuously variable in both horizontal-and vertical dimensions. In addition, ActionMedia-II.RTM. subsystem 108 does not provide display scaling with interpolation of all three video components in both the horizontal and vertical dimensions. This is due, in part, to the fact that the pixel processor of ActionMedia-II.RTM. subsystem 108 does not have the bandwidth to interpolate as it performs the copy/scale function. Nor does the pixel processor of ActionMedia-II.RTM. subsystem 108 have the bandwidth to scale up during normal processing rates of 30 frames per second.
In addition, ActionMedia-II.RTM. subsystem 108 contains display processor 201 and three gate arrays (capture/VRAM controller 204, host interface 214, and keying/audio processor 220). Furthermore, to meet the data bandwidth requirements for video system 100 and to store separate and entire bit streams for the compressed video data and bitmaps for the decompressed video data and the scaled video data, ActionMedia-II.RTM. subsystem 108 contains two megabytes of dual-port VRAM 208.
It is desirable to provide a video system for the capture, compression, decompression, and display of video images in a personal computer environment that does not create and store complete scaled bitmaps to memory before displaying the scaled data. Such a video system preferably scales only pixel data corresponding to the active video window pixel region. In addition, the display scaling implemented by the video system is preferably continuously variable in both horizontal and vertical dimensions. Moreover, the video system preferably provides display scaling with interpolation of all three video components in both the horizontal and vertical dimensions at normal processing rates of 30 frames per second. Furthermore, it is desirable that the video system not have multiple gate arrays and a display processor. It is also desirable that the video system not have a relatively large dual-port memory device.
It is accordingly an object of this invention to overcome the limitations of the known art and to provide a video system for the capture, compression, decompression, and display of video images in a personal computer environment, where the video system does not create and store complete scaled bitmaps to memory before displaying the scaled data.
It is a further object of the present invention to provide such a video system that scales only pixel data corresponding to the active video window pixel region.
It is a further object of the present invention to provide such a video system that implements continuously variable display scaling in both horizontal and vertical dimensions.
It is a further object of the present invention to provide such a video system that implements display scaling with interpolation of all three video components in both the horizontal and vertical dimensions at normal processing rates of 30 frames per second.
It is a further object of the present invention to provide a video system that meets the above-listed objects without having a relatively large dual-port memory device such as a VRAM.
It is a further object of the present invention to provide a video system that meets the above-listed objects without having multiple separate gate arrays and a separate display processor.
It is a further object of the present invention to provide such a video system with a relatively low gate count and therefore a lower cost.
Further objects and advantages of this invention will become apparent from the detailed description of a preferred embodiment which follows.